Optimal circuit clustering for delay minimization under a more general delay model
نویسندگان
چکیده
but the main arguments hold and hierarchical DRC programs have been replacing flat DRC programs in the market [4]. For hierarchical timing analysis, one set of simplifying assumptions might be that the design contains only one clock, no transparent latches, and no purely combinatorial paths through cells. Starting with the leaf cells, analyze all paths between flip-flops and report any errors, then generate abstracts. There are (at least) two possible strategies for abstracts: deriving a required time and/or an arrival time for each pin, or including in the abstract all logic between each pin and the first clocked element. In either case then, the algorithm works its way up the hierarchy , substituting abstracts for the lower level cells, doing the timing analysis, and then computing the abstracts for use by the next higher level. For either abstraction strategy, the size of the abstract will be proportional to the number of pins. From Rent's rule [6], the number of pins on a block of n primitives is proportional to n a , where a is Rent's exponent and ranges from about 0.5 to 0.7. Therefore, to get linear time analysis overall, timing analysis and abstract generation must complete in time n b , where b < 1=a (roughly 1.42 if a = 0:7). Timing analysis, which is nominally O(N), easily satisfies this constraint. Under real world conditions, however, hierarchical timing analysis is not uniformly advantageous. Multiple clocks, or combinatorial paths through blocks, can cause the timing abstract to grow more quickly than the number of pins, and, in fact, can result in a > 1. The presence of transparent latches can make the abstract larger and harder to compute. It can be very difficult and time consuming to generate a correct abstract for a cell with false and multicycle paths, especially if these paths cross hierarchical boundaries. Therefore, although hierarchical timing analysis is certainly used, it is mainly because of the other advantages mentioned in the introduction, not because of the efficiency arguments of this paper. VI. CONCLUSION Under conditions that are sometimes achievable in practice, hierarchical checking has performance O(N) in the size of the expanded hierarchy, which is the best order possible. APPENDIX Why is hierarchical DRC NP-complete? Here's a sketch of the proof from [2]. The integer knapsack problem is known to be NP-complete. these that adds up to S ? Hierarchical DRC is a more complex …
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عنوان ژورنال:
- IEEE Trans. on CAD of Integrated Circuits and Systems
دوره 22 شماره
صفحات -
تاریخ انتشار 2003